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1 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d S2018 ? 17 x 17 3.2 gbit/s differential crosspoint switch device specification features ? sige bicmos technology ? 17 x 17 differential crosspoint switch ? broadcast and multicast switching capability ? differential 200 mv to 1400 mv input data ? differential 200 mv to 1300 mv programmable output swing ? up to 3.2 gbps nrz data rate ? lvttl configuration controls ? internal 100 w line-to-line terminations on high- speed differential inputs ? reconfigurable without disturbing operation ? 35 mm x 35 mm 352 pin sbga package ? +3.3 v only power supply ? 4 w typical power dissipation with 800 mv output swing ? complies with bellcore and itu-t standard applications ? dense wavelength division multiplexing (dwdm) systems ? internet switches ? digital video ? digital demultiplexing ? microwave or fiber-optic data distribution ? high-speed automatic test equipment ? datacom or telecom switching general description the S2018 is a high speed 17 x 17 differential cross- point switch with full broadcast capability. any of its 17 differential lvpecl input signal pairs can be con- nected to any or all of its 17 differential cml output signal pairs. the differential 10k lvpecl logic data path makes the part ideal for high-speed applications. the differ- ential nature of the data path is retained throughout the crosspoint structure to minimize data distortion and to handle nrz data rates up to 3.2 gigabits per second. the high-speed serial inputs to the S2018 are internally biased and have internal 100 w line-to- line terminations. lvttl configuration controls simplify interfacing to slower speed circuitry. once a new configuration has been entered into the configuration register file, the S2018 can be completely reconfigured by pulsing the confign input. figure 1 shows a system block diagram incorporat- ing the S2018 with amcc serial backplane devices. figure 2 shows the basic operation of the switch. figure 1. system block diagram . . . . . . . . 16 0 s2062 s2004 . . . . . . . . 0 16 s2064 s2002 S2018 crosspoint switch crosspoint control ( p & dram)
2 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d figure 2. functional block diagram diff. lvpecl input buffers diff. cml output buffers 17 x 17 differential crosspoint 34 34 din0p din16p dout0p dout16p active configuration latch 85 17 x 5 configuration register file 85 iaddr[4:0] data 17 5:17 decode en confign loadn csn oaddr[4:0] 5 5 select dout0n dout16n din0n din16n vadjust3 vadjust2 vadjust1 vcshigh f f i d t u p n i 4 r d d a i3 r d d a i2 r d d a i1 r d d a i0 r d d a i f f i d t u p t u o 4 r d d a o3 r d d a o2 r d d a o1 r d d a o0 r d d a o 0 n i d 1 n i d 2 n i d 3 n i d 4 n i d 5 n i d 6 n i d 7 n i d 8 n i d 9 n i d 0 1 n i d 1 1 n i d 2 1 n i d 3 1 n i d 4 1 n i d 5 1 n i d 6 1 n i d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x 0 t u o d 1 t u o d 2 t u o d 3 t u o d 4 t u o d 5 t u o d 6 t u o d 7 t u o d 8 t u o d 9 t u o d 0 1 t u o d 1 1 t u o d 2 1 t u o d 3 1 t u o d 4 1 t u o d 5 1 t u o d 6 1 t u o d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x table 1. input/output address of S2018 note: x denotes don't care
3 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d data transfer for each configured connection between a differen- tial input pair and an enabled output pair, any data appearing at the input pair will be passed immedi- ately through to the output pair. configuration the S2018 can be selectively configured one output pair at a time, or any number of output pairs simulta- neously. configuration data is stored in 17 registers, one register for each output pair. the data in these 17 configurations register makes up the configura- tion register file. as shown in figure 2, the configura- tion data is passed in parallel from all 17 registers to a latch, which holds the active switch configuration. this two-stage arrangement allows one or more out- put pairs to be configured simultaneously. a chip select pin (csn) is provided to simplify interfacing this switch to the system microprocessor. the S2018 minimizes the configuration time through the use of the active configuration latch. while the switch is operational, and prior to the time at which it must be reconfigured, a new configuration is loaded into the configuration register file. once the configu- ration register file contains the desired connection information, the contents of the registers are trans- ferred in parallel to the active configuration latch by the confign strobe. to connect an output to a given input, the output to be configured is selected using the oaddr[4:0] (oaddr4=msb) inputs. see table 1. with the out- put configuration register selected, the desired input selection must be provided in the iaddr[4:0] (iaddr4=msb) inputs. the iaddr[4:0] information is stored into the selected output configuration regis- ter by the loadn strobe. the configuration process is described by the flow chart in figure 5. the active configuration latch can be made transpar- ent by activating the confign input. when this is done, changes strobed into the output pair configu- ration registers by the loadn input pair will be passed immediately to the switch. the S2018 supports both broadcast and multicast operation: any of the 17 differential input pairs can be connected to any or all of the 17 differential out- put pairs. output swing adjust the S2018 output swing can be adjusted by con- necting one or more of the vadjustx pins to the vcshigh pin according to table 2. note that as the output swing is increased, the power dissipated by the part is proportionally increased (see table 10). figure 3. data transfer waveforms figure 4. reconfiguration waveforms 1 t s u j d a v2 t s u j d a v3 t s u j d a v) . f f i d p p v m ( x x t u o d t o t o t o t o t t o o t t o o o t t t t 0 4 2 0 4 4 0 0 6 0 8 7 0 4 9 0 0 1 1 0 6 2 1 table 2. output swing adjust pin settings note: t = ties pin(s) vadjustx to pin vcshigh o = open t cfdo t lddo t dido di mpw din[16:0]p/n dout[16:0]p/n confign csn loadn a ab cd e bcde t csdo t suia ld mpw t hia t sulc cf mpw t suoa t hoa oaddr[4:0] iaddr[4:0] csn loadn valid valid confign t sucs t hcs
4 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d activate csn configure oaddr[4:0] to desired output. see table 1. configure iaddr[4:0] to desired input. see table 1. strobe loadn to store the input address (iaddr[4:0]) in the section of the configuration register file pointed to by the output register (oaddr[4:0]) configure another output? strobe confign to store all connections to the active configuration latch yes no figure 5. S2018 configuration flow chart
5 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 3. data transfer timing 1,2 r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c t o d i d n / p ] 0 : 6 1 [ n i d m o r f y a l e d n o i t a g a p o r p n / p ] 0 : 6 1 [ t u o d o t 5 . 1s n t o d f c f o e g d e g n i l l a f m o r f y a l e d n o i t a g a p o r p d i l a v n / p ] 0 : 6 1 [ t u o d o t n g i f n o c 3s n t o d d l f o e g d e g n i l l a f m o r f y a l e d n o i t a g a p o r p d i l a v n / p ] 0 : 6 1 [ t u o d o t n d a o l ) w o l d l e h s i n g i f n o c n e h w ( 4s n t o d s c f o e g d e g n i l l a f m o r f y a l e d n o i t a g a p o r p n e h w ( d i l a v n / p ] 0 : 6 1 [ t u o d o t n s c ) w o l d l e h s i n g i f n o c 0 1s n i d w p m n / p ] 0 : 5 1 [ n i d f o h t d i w e s l u p0 8 2s p 6 1 i d w p m n / p 6 1 n i d f o h t d i w e s l u p0 9s p f x a m e t a r a t a d2 . 3s p b g t s m r r e t t i j t u p n i y n a , n o i t a l u m u c c a r e t t i j m o d n a r : t a t u p t u o y n a o t s p b g 2 . 3 s p b g 5 . 2 s p b g 5 . 1 9 . 1 9 . 1 9 . 1 3 3 3 s p r e t t i j t u p t u o s m r h t i w d e t a l u m u c c a n o d e t s e t . e d o c 7 . 8 2 k . s i s a b e l p m a s a t r e t t i jj d y n a , n o i t a l u m u c c a r e t t i j c i t s i n i m r e t e d : t u p t u o y n a o t t u p n i s p b g 2 . 3 s p b g 5 . 2 s p b g 5 . 1 9 1 8 1 8 1 7 2 7 2 7 2 s p t u p t u o c i t s i n i m r e t e d d e t a l u m u c c a r e t t i j d e t s e t . n r e t t a p 5 . 8 2 k . s i s a b e l p m a s a n o . k a e p - o t - k a e p e n o w e k s m o r f s h t a p n e e w t e b w e k s t s a c d a o r b e l p i t l u m o t ) ] 0 : 5 1 [ n i d ( t u p n i e n o y n a s e d u l c x e . ) ] 0 : 5 1 [ t u o d ( s t u p t u o . ] 6 1 [ t u o d d n a ] 6 1 [ n i d 0 4 1s p l l a w e k s e l p i t l u m m o r f s h t a p n e e w t e b w e k s s t u p t u o e l p i t l u m o t ) ] 0 : 5 1 [ n i d ( s t u p n i d n a ] 6 1 [ n i d s e d u l c x e . ) ] 0 : 5 1 [ t u o d ( . ] 6 1 [ t u o d 0 5 1s p 6 1 e n o w e k s m o r f s h t a p n e e w t e b w e k s t s a c d a o r b e l p i t l u m o t ) ] 0 : 6 1 [ n i d ( t u p n i e n o y n a . ) ] 0 : 6 1 [ t u o d ( s t u p t u o 0 0 3s p 6 1 l l a w e k s e l p i t l u m m o r f s h t a p n e e w t e b w e k s s t u p t u o e l p i t l u m o t ) ] 0 : 6 1 [ n i d ( s t u p n i . ) ] 0 : 6 1 [ t u o d ( 0 6 4s p t r t , f ) % 0 8 o t % 0 2 ( e t a r e g d e t u p t u o5 2 1s p0 0 1 w . e n i l - o t - e n i l 1. all data transfer timing measured from the crossing point of the differential inputs to the crossing point of the differenti al outputs. 2. all data measured with 800 mvpp swing.
6 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 4. reconfiguration timing 1 1. all reconfiguration timing measured from the 1.5 v point on the lvttl signals. r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n u t a i u s n d a o l f o e g d e g n i l l a f e r o f e b ] 0 : 4 [ r d d a i f o e m i t p u t e s0s n t a i h n d a o l f o e g d e g n i s i r r e t f a ] 0 : 4 [ r d d a i f o e m i t d l o h2s n t a o u s n d a o l f o e g d e g n i l l a f e r o f e b ] 0 : 4 [ r d d a o f o e m i t p u t e s0s n t a o h n d a o l f o e g d e g n i s i r r e t f a ] 0 : 4 [ r d d a o f o e m i t d l o h2s n t c l u s f o e g d e g n i l l a f e h t t a h t o s n g i f n o c o t n d a o l f o e m i t p u t e s n o i t a r u g i f n o c e r t r a t s l l i w n g i f n o c 2s n t s c u s n d a o l f o e g d e g n i l l a f e r o f e b n s c f o e m i t p u t e s0s n t s c h n d a o l f o e g d e g n i s i r r e t f a n s c f o e m i t d l o h0s n d l w p m n d a o l f o w o l h t d i w e s l u p2s n f c w p m n g i f n o c f o w o l h t d i w e s l u p2s n f x a m n g i f n o c , d a o l 0 0 1z h m
7 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 5. pin assignment and descriptions e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d p 6 1 n i d n 6 1 n i d dn ip 5 1 dn in 5 1 dn ip 4 1 dn in 4 1 dn ip 3 1 dn in 3 1 dn ip 2 1 dn in 2 1 dn ip 1 1 dn in 1 1 dn ip 0 1 dn in 0 1 dn ip 9 dn in 9 dn ip 8 n 8 n i d p 7 n i d n 7 n i d p 6 n i d n 6 n i d p 5 n i d n 5 n i d p 4 n i d n 4 n i d p 3 n i d n 3 n i d p 2 n i d n 2 n i d p 1 n i d n 1 n i d p 0 n i d n 0 n i d . f f i d l c e p v l i2 j 1 j 2 g 1 g 2 e 1 e 4 a 4 b 6 a 6 b 8 a 8 b 0 1 a 0 1 b 2 1 a 2 1 b 4 1 a 4 1 b 3 1 e a 3 1 f a 1 1 e a 1 1 f a 9 e a 9 f a 7 e a 7 f a 5 e a 5 f a 2 b a 1 b a 2 y 1 y 2 v 1 v 0 0 1 h t i w d e t a n i m r e t y l l a n r e t n i . l a i t n e r e f f i d . a t a d t u p n i w - e n i l v o t d e s a i b c d y l l a n r e t n i . e n i l - o t c c . v 4 8 . 0 - 4 r d d a o 3 r d d a o 2 r d d a o 1 r d d a o 0 r d d a o l t t v li1 p 2 r 1 r 2 t 1 t n o i t a r u g i f n o c t u p t u o n a t c e l e s o t d e s u . s s e r d d a t u p t u o . 1 e l b a t e e s . e l i f r e t s i g e r n o i t a r u g i f n o c e h t n i r e t s i g e r 4 r d d a i 3 r d d a i 2 r d d a i 1 r d d a i 0 r d d a i l t t v li2 n 2 m 1 m 2 l 1 l o t t c e n n o c o t r i a p t u p n i e h t s t c e l e s ] 0 : 4 [ r d d a i . s s e r d d a t u p n i . 1 e l b a t e e s . ] 0 : 4 [ r d d a o y b d e t c e l e s r i a p t u p t u o e h t n d a o ll t t v li2 pe h t s e r o t s , e v i t c a n e h w . w o l e v i t c a . e b o r t s d a o l n o i t a r u g i f n o c e h t o t n i ] 0 : 4 [ r d d a i n i a t a d n o i t a r u g i f n o c . e l i f r e t s i g e r n g i f n o cl t t v li3 ns d a o l l e l l a r a p , e v i t c a n e h w . w o l e v i t c a . e b o r t s n o i t a r u g i f n o c e v i t c a e h t o t n i e l i f r e t s i g e r n o i t a r u g i f n o c e h t f o s t n e t n o c e h t . h c t a l n o i t a r u g i f n o c h g i h s c vi3 2 f at e s o t ) s ( n i p x t s u j d a v o t e i t . t s u j d a g n i w s e g a t l o v t u p t u o . s l i a t e d r o f 2 e l b a t e e s . g n i w s e g a t l o v t u p t u o
8 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 5. pin assignment and descriptions (continued) e m a n n i pl e v e lo / i# n i pn o i t p i r c s e d 1 t s u j d a v 2 t s u j d a v 3 t s u j d a v o3 2 e a 5 2 c a 6 2 c a , h g i h s c v o t d e i t y l e v i t c e l e s , s n i p e e r h t e s e h t . t s u j d a e g a t l o v . g n i w s e g a t l o v t u p t u o e h t s t e s h c i h w t u p t u o d e d o c a e t a e r c . 2 e l b a t e e s n s cl t t v li1 nl l i w l a n g i s n d a o l e h t , e v i t c a n i n e h w . w o l e v i t c a . t c e l e s p i h c , e v i t c a n e h w . d e w o l l a e b t o n l l i w s e s s e r d d a w e n . d e r o n g i e b . d e i f i c e p s s a e t a r e p o l l i w 8 1 0 2 s e h t p 6 1 t u o d n 6 1 t u o d dt u op 5 1 dt u on 5 1 dt u op 4 1 dt u on 4 1 dt u op 3 1 dt u on 3 1 dt u op 2 1 dt u on 2 1 dt u op 1 1 dn 1 1 t u o dt u op 0 1 dt u on 0 1 dt u op 9 dt u on 9 dt u op 8 n 8 t u o d p 7 t u o d n 7 t u o d p 6 t u o d n 6 t u o d p 5 t u o d n 5 t u o d p 4 t u o d n 4 t u o d p 3 t u o d n 3 t u o d p 2 t u o d n 2 t u o d p 1 t u o d n 1 t u o d p 0 t u o d n 0 t u o d . f f i d l m c o6 2 n 5 2 n 6 2 l 5 2 l 6 2 j 5 2 j 6 2 g 5 2 g 6 2 e 5 2 e 3 2 b 3 2 a 1 2 b 1 2 a 9 1 b 9 1 a 7 1 b 7 1 a 6 1 f a 6 1 e a 8 1 f a 8 1 e a 0 2 f a 0 2 e a 2 2 f a 2 2 e a 6 2 a a 5 2 a a 6 2 w 5 2 w 6 2 u 5 2 u 6 2 r 5 2 r . l a i t n e r e f f i d . a t a d t u p t u o
9 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 6. power and ground signals e m a n n i py t i t n a u qo / i# n i pn o i t p i r c s e d t u p n i c c v7 2, 2 b , 1 b , 1 1 a , 2 a , 1 a , 5 1 c , 1 1 c , 3 c , 1 1 b , 2 f , 1 f , 5 1 d , 1 1 d , 4 d , 2 c a , 1 c a , 4 v , 3 v , 3 1 c a , 9 c a , 4 c a , 2 e a , 1 e a , 9 d a , 3 d a 2 f a , 1 f a d e e p s h g i h r o f r e w o p . y l p p u s r e w o p v 3 . 3 + . s t u p n i t u p n i d n g0 6, 3 b , 4 2 a , 5 1 a , 3 a , 2 c , 1 c , 4 2 b , 5 1 b , 5 2 c , 3 2 c , 2 1 c , 4 c , 4 2 d , 2 1 d , 3 d , 6 2 c , 4 f , 3 f , 6 2 d , 5 2 d , 3 m , 4 l , 3 l , 4 k , 3 k , 3 t , 4 r , 3 r , 4 n , 4 m , 4 u , 3 u , 2 u , 1 u , 4 t , 4 w , 3 w , 2 w , 1 w , 4 2 c a , 0 1 c a , 3 c a , 4 d a , 2 d a , 1 d a , 3 2 d a , 3 1 d a , 0 1 d a , 3 e a , 6 2 d a , 5 2 d a , 4 2 e a , 0 1 e a , 4 e a , 4 f a , 3 f a , 6 2 e a 5 2 f a , 4 2 f a , 0 1 f a . s t u p n i d e e p s h g i h r o f d n u o r g c c v l t t6 1, 1 k , 4 2 j , 6 1 d , 6 1 c , 3 2 c a , 7 c a , 3 p , 2 k , 4 1 e a , 4 2 d a , 7 d a , 4 1 f a , 5 2 e a , 7 1 e a 6 2 f a , 7 1 f a . s t u p n i l t t r o f r e w o p . y l p p u s r e w o p v 3 . 3 + d n g l t t4 1, 3 2 j , 4 j , 3 j , 6 1 b , 6 1 a , 4 1 c a , 8 c a , 4 p , 4 1 d a , 8 d a , 7 1 c a 8 f a , 8 e a , 7 1 d a . s t u p n i l t t r o f d n u o r g e r o c c c v1 3, 5 b , 3 1 a , 9 a , 7 a , 5 a , 7 c , 5 c , 3 1 b , 9 b , 7 b , 1 d , 7 1 c , 3 1 c , 9 c , 3 1 d , 9 d , 7 d , 5 d , 2 d , 4 y , 3 y , 4 2 r , 4 g , 3 g , 1 1 c a , 5 c a , 3 b a , 5 1 e a , 1 1 d a , 5 d a 5 1 f a . r e w o p y r t i u c r i c e r o c . y l p p u s r e w o p v 3 . 3 + e r o c d n g1 3, 4 1 c , 0 1 c , 8 c , 6 c , 4 1 d , 0 1 d , 8 d , 6 d , 2 h , 1 h , 4 e , 3 e , 7 1 d , 1 a a , 3 2 r , 4 h , 3 h , 4 b a , 4 a a , 3 a a , 2 a a , 5 1 c a , 2 1 c a , 6 c a , 5 1 d a , 2 1 d a , 6 d a , 6 f a , 2 1 e a , 6 e a 2 1 f a . d n u o r g y r t i u c r i c e r o c
10 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 6. power and ground signals (continued) e m a n n i py t i t n a u qo / i# n i pn o i t p i r c s e d t s u j d a c c v1 4 2 b a. t u p n i t s u j d a v r o f r e w o p t s u j d a d n g1 3 2 b a. t u p n i t s u j d a v r o f d n u o r g c c v0 5, 5 2 a , 2 2 a , 0 2 a , 8 1 a , 2 2 b , 0 2 b , 8 1 b , 6 2 a , 0 2 c , 8 1 c , 6 2 b , 5 2 b , 3 2 d , 0 2 d , 8 1 d , 4 2 c , 6 2 f , 5 2 f , 4 2 f , 3 2 f , 4 2 k , 3 2 k , 4 2 h , 3 2 h , 4 2 m , 3 2 m , 6 2 k , 5 2 k , 4 2 p , 3 2 p , 6 2 m , 5 2 m , 6 2 t , 5 2 t , 4 2 t , 3 2 t , 6 2 v , 5 2 v , 4 2 v , 3 2 v , 3 2 a a , 6 2 y , 5 2 y , 8 1 c a , 6 1 c a , 4 2 a a , 0 2 d a , 8 1 d a , 0 2 c a 2 2 d a . s t u p t u o d e e p s h g i h r o f y l p p u s r e w o p v 3 . 3 + d n g6 3, 9 1 d , 2 2 c , 1 2 c , 9 1 c , 4 2 e , 3 2 e , 2 2 d , 1 2 d , 6 2 h , 5 2 h , 4 2 g , 3 2 g , 4 2 n , 3 2 n , 4 2 l , 3 2 l , 4 2 u , 3 2 u , 6 2 p , 5 2 p , 4 2 y , 3 2 y , 4 2 w , 3 2 w , 9 1 c a , 6 2 b a , 5 2 b a , 6 1 d a , 2 2 c a , 1 2 c a , 9 1 e a , 1 2 d a , 9 1 d a 1 2 f a , 9 1 f a , 1 2 e a . s t u p t u o d e e p s h g i h r o f d n u o r g
11 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d figure 6. S2018 pinout (top view) 1 2 3 4 5 6 7 8 9 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 0 2 1 2 2 2 3 2 4 2 5 2 6 2 a c c v t u p n i c c v t u p n i d n g t u p n i p 3 1 n i d c c v e r o c p 2 1 n i d c c v e r o c p 1 1 n i d c c v e r o c p 0 1 n i d c c v t u p n i p 9 n i d c c v e r o c p 8 n i d d n g t u p n i d n g l t tn 8 t u o dc c vn 9 t u o dc c vn 0 1 t u o dc c vn 1 1 t u o d d n g t u p n i c c vc c v b c c v t u p n i c c v t u p n i d n g t u p n i n 3 1 n i d c c v e r o c n 2 1 n i d c c v e r o c n 1 1 n i d c c v e r o c n 0 1 n i d c c v t u p n i n 9 n i d c c v e r o c n 8 n i d d n g t u p n i d n g l t tp 8 t u o dc c vp 9 t u o dc c vp 0 1 t u o dc c vp 1 1 t u o d d n g t u p n i c c vc c v c d n g t u p n i d n g t u p n i c c v t u p n i d n g t u p n i c c v e r o c d n g e r o c c c v e r o c d n g e r o c c c v e r o c d n g e r o c c c v t u p n i d n g t u p n i c c v e r o c d n g e r o c c c v t u p n i c c v l t t c c v e r o c c c vd n gc c vd n gd n g d n g t u p n i c c v d n g t u p n i d n g t u p n i d c c v e r o c c c v e r o c d n g t u p n i c c v t u p n i c c v e r o c d n g e r o c c c v e r o c d n g e r o c c c v e r o c d n g e r o c c c v t u p n i d n g t u p n i c c v e r o c d n g e r o c c c v t u p n i c c v l t t d n g e r o c c c vd n gc c vd n gd n gc c v d n g t u p n i d n g t u p n i d n g t u p n i e n 4 1 n i dp 4 1 n i d d n g e r o c d n g e r o c d n gd n gn 2 1 t u o dp 2 1 t u o d f c c v t u p n i c c v t u p n i d n g t u p n i d n g t u p n i c c vc c vc c vc c v g n 5 1 n i dp 5 1 n i d c c v e r o c c c v e r o c d n gd n gn 3 1 t u o dp 3 1 t u o d h d n g e r o c d n g e r o c d n g e r o c d n g e r o c c c vc c vd n gd n g j n 6 1 n i dp 6 1 n i dd n g l t td n g l t t d n g l t tc c v l t tn 4 1 t u o dp 4 1 t u o d k c c v l t tc c v l t t d n g t u p n i d n g t u p n i c c vc c vc c vc c v l 0 r d d a i1 r d d a i d n g t u p n i d n g t u p n i d n gd n gn 5 1 t u o dp 5 1 t u o d m 2 r d d a i3 r d d a i d n g t u p n i d n g t u p n i c c vc c vc c vc c v n n s c4 r d d a in g i f n o c d n g t u p n i d n gd n gn 6 1 t u o dp 6 1 t u o d p 4 r d d a on d a o lc c v l t td n g l t t c c vc c vd n gd n g r 2 r d d a o3 r d d a o d n g t u p n i d n g t u p n i d n g e r o c c c v e r o c n 0 t u o dp 0 t u o d t 0 r d d a o1 r d d a o d n g t u p n i d n g t u p n i c c vc c vc c vc c v u d n g t u p n i d n g t u p n i d n g t u p n i d n g t u p n i d n gd n gn 1 t u o dp 1 t u o d v n 0 n i dp 0 n i d c c v t u p n i c c v t u p n i c c vc c vc c vc c v w d n g t u p n i d n g t u p n i d n g t u p n i d n g t u p n i d n gd n gn 2 t u o dp 2 t u o d y n 1 n i dp 1 n i d c c v e r o c c c v e r o c d n gd n gc c vc c v a a d n g e r o c d n g e r o c d n g e r o c d n g e r o c c c vc c vn 3 t u o dp 3 t u o d b a n 2 n i dp 2 n i d c c v e r o c d n g e r o c d n g t s u j d a c c v t s u j d a d n gd n g c a c c v t u p n i c c v t u p n i d n g t u p n i c c v t u p n i c c v e r o c d n g e r o c c c v l t td n g l t t c c v t u p n i d n g t u p n i c c v e r o c d n g e r o c c c v t u p n i d n g l t t d n g e r o c c c vd n g l t tc c vd n gc c vd n gd n gc c v l t t d n g t u p n i - t s u j d a v 2 - t s u j d a v 3 d a d n g t u p n i d n g t u p n i c c v t u p n i d n g t u p n i c c v e r o c d n g e r o c c c v l t td n g l t t c c v t u p n i d n g t u p n i c c v e r o c d n g e r o c d n g t u p n i d n g l t t d n g e r o c d n gd n g l t tc c vd n gc c vd n gc c v d n g t u p n i c c v l t t d n g t u p n i d n g t u p n i e a c c v t u p n i c c v t u p n i d n g t u p n i d n g t u p n i p 3 n i d d n g e r o c p 4 n i dd n g l t tp 5 n i d d n g t u p n i p 6 n i d d n g e r o c p 7 n i dc c v l t t c c v e r o c n 7 t u o dc c v l t tn 6 t u o dd n gn 5 t u o dd n gn 4 t u o d - t s u j d a v 1 d n g t u p n i c c v l t t d n g t u p n i f a c c v t u p n i c c v t u p n i d n g t u p n i d n g t u p n i n 3 n i d d n g e r o c n 4 n i dd n g l t tn 5 n i d d n g t u p n i n 6 n i d d n g e r o c n 7 n i dc c v l t t c c v e r o c p 7 t u o dc c v l t tp 6 t u o dd n gp 5 t u o dd n gp 4 t u o dh g i h s c v d n g t u p n i d n g t u p n i c c v l t t tb - 352 pin sbga (top view)
12 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d figure 7. S2018 pinout (bottom view) 6 2 5 2 4 2 3 2 2 2 1 2 0 2 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 9 8 7 6 5 4 3 2 1 c c vc c v d n g t u p n i n 1 1 t u o dc c vn 0 1 t u o dc c vn 9 t u o dc c vn 8 t u o dd n g l t t d n g t u p n i p 8 n i d c c v e r o c p 9 n i d c c v t u p n i p 0 1 n i d c c v e r o c p 1 1 n i d c c v e r o c p 2 1 n i d c c v e r o c p 3 1 n i d d n g t u p n i c c v t u p n i c c v t u p n i a c c vc c v d n g t u p n i p 1 1 t u o dc c vp 0 1 t u o dc c vp 9 t u o dc c vp 8 t u o dd n g l t t d n g t u p n i n 8 n i d c c v e r o c n 9 n i d c c v t u p n i n 0 1 n i d c c v e r o c n 1 1 n i d c c v e r o c n 2 1 n i d c c v e r o c n 3 1 n i d d n g t u p n i c c v t u p n i c c v t u p n i b d n g t u p n i d n g t u p n i c c v d n g t u p n i d n gd n gc c vd n gc c v c c v e r o c c c v l t t c c v t u p n i d n g e r o c c c v e r o c d n g t u p n i c c v t u p n i d n g e r o c c c v e r o c d n g e r o c c c v e r o c d n g e r o c c c v e r o c d n g t u p n i c c v t u p n i d n g t u p n i d n g t u p n i c d n g t u p n i d n g t u p n i d n g t u p n i c c vd n gd n gc c vd n gc c v d n g e r o c c c v l t t c c v t u p n i d n g e r o c c c v e r o c d n g t u p n i c c v t u p n i d n g e r o c c c v e r o c d n g e r o c c c v e r o c d n g e r o c c c v e r o c c c v t u p n i d n g t u p n i c c v e r o c c c v e r o c d p 2 1 t u o dn 2 1 t u o dd n gd n g d n g e r o c d n g e r o c p 4 1 n i dn 4 1 n i d e c c vc c vc c vc c v d n g t u p n i d n g t u p n i c c v t u p n i c c v t u p n i f p 3 1 t u o dn 3 1 t u o dd n gd n g c c v e r o c c c v e r o c p 5 1 n i dn 5 1 n i d g d n gd n gc c vc c v d n g e r o c d n g e r o c d n g e r o c d n g e r o c h p 4 1 t u o dn 4 1 t u o dc c v l t td n g l t t d n g l t td n g l t tp 6 1 n i dn 6 1 n i d j c c vc c vc c vc c v d n g t u p n i d n g t u p n i c c v l t tc c v l t t k p 5 1 t u o dn 5 1 t u o dd n gd n g d n g t u p n i d n g t u p n i 1 r d d a i0 r d d a i l c c vc c vc c vc c v d n g t u p n i d n g t u p n i 3 r d d a i2 r d d a i m p 6 1 t u o dn 6 1 t u o dd n gd n g d n g t u p n i n g i f n o c4 r d d a in s c n d n gd n gc c vc c v d n g l t tc c v l t tn d a o l4 r d d a o p p 0 t u o dn 0 t u o d c c v e r o c d n g e r o c d n g t u p n i d n g t u p n i 3 r d d a o2 r d d a o r c c vc c vc c vc c v d n g t u p n i d n g t u p n i 1 r d d a o0 r d d a o t p 1 t u o dn 1 t u o dd n gd n g d n g t u p n i d n g t u p n i d n g t u p n i d n g t u p n i u c c vc c vc c vc c v c c v t u p n i c c v t u p n i p 0 n i dn 0 n i d v p 2 t u o dn 2 t u o dd n gd n g d n g t u p n i d n g t u p n i d n g t u p n i d n g t u p n i w c c vc c vd n gd n g c c v e r o c c c v e r o c p 1 n i dn 1 n i d y p 3 t u o dn 3 t u o dc c vc c v d n g e r o c d n g e r o c d n g e r o c d n g e r o c a a d n gd n g c c v t s u j d a d n g t s u j d a d n g e r o c c c v e r o c p 2 n i dn 2 n i d b a - t s u j d a v 3 - t s u j d a v 2 d n g t u p n i c c v l t td n gd n gc c vd n gc c vd n g l t tc c v d n g e r o c d n g l t t c c v t u p n i d n g e r o c c c v e r o c d n g t u p n i c c v t u p n i d n g l t tc c v l t t d n g e r o c c c v e r o c c c v t u p n i d n g t u p n i c c v t u p n i c c v t u p n i c a d n g t u p n i d n g t u p n i c c v l t t d n g t u p n i c c vd n gc c vd n gc c vd n g l t td n g d n g e r o c d n g l t t d n g t u p n i d n g e r o c c c v e r o c d n g t u p n i c c v t u p n i d n g l t tc c v l t t d n g e r o c c c v e r o c d n g t u p n i c c v t u p n i d n g t u p n i d n g t u p n i d a d n g t u p n i c c v l t t d n g t u p n i - t s u j d a v 1 n 4 t u o dd n gn 5 t u o dd n gn 6 t u o dc c v l t tn 7 t u o d c c v e r o c c c v l t tp 7 n i d d n g e r o c p 6 n i d d n g t u p n i p 5 n i dd n g l t tp 4 n i d d n g e r o c p 3 n i d d n g t u p n i d n g t u p n i c c v t u p n i c c v t u p n i e a c c v l t t d n g t u p n i d n g t u p n i h g i h s c vp 4 t u o dd n gp 5 t u o dd n gp 6 t u o dc c v l t tp 7 t u o d c c v e r o c c c v l t tn 7 n i d d n g e r o c n 6 n i d d n g t u p n i n 5 n i dd n g l t tn 4 n i d d n g e r o c n 3 n i d d n g t u p n i d n g t u p n i c c v t u p n i c c v t u p n i f a tb - 352 pin sbga (bottom view)
13 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d figure 8. 35 mm x 35 mm 352 pin sbga package
14 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d r e w o p e g a k c a p x a mr e w o p e g a k c a p x a m r e w o p e g a k c a p x a m r e w o p e g a k c a p x a mr e w o p e g a k c a p x a m ) w () w ( ) w ( ) w () w ( w o l f r i aw o l f r i a w o l f r i a w o l f r i aw o l f r i a ) m p f l () m p f l ( ) m p f l ( ) m p f l () m p f l ( q q q q q a ja j a j a ja j ) w / c ? () w / c ? ( ) w / c ? ( ) w / c ? () w / c ? ( q q q q q c jc j c j c jc j ) w / c ? () w / c ? ( ) w / c ? ( ) w / c ? () w / c ? ( 4 4 . 300 . 6 12 7 . 0 9 7 . 30 0 15 . 4 12 7 . 0 0 4 . 40 0 25 . 2 12 7 . 0 r e w o p e g a k c a p x a mr e w o p e g a k c a p x a m r e w o p e g a k c a p x a m r e w o p e g a k c a p x a mr e w o p e g a k c a p x a m ) w () w ( ) w ( ) w () w ( w o l f r i aw o l f r i a w o l f r i a w o l f r i aw o l f r i a ) m p f l () m p f l ( ) m p f l ( ) m p f l () m p f l ( q q q q q a ja j a j a ja j d - f n 3 6 2 s t h h t i wd - f n 3 6 2 s t h h t i w d - f n 3 6 2 s t h h t i w d - f n 3 6 2 s t h h t i wd - f n 3 6 2 s t h h t i w ) w / c ? ( k n i s t a e h) w / c ? ( k n i s t a e h ) w / c ? ( k n i s t a e h ) w / c ? ( k n i s t a e h) w / c ? ( k n i s t a e h d - f n 3 6 2 s t hd - f n 3 6 2 s t h d - f n 3 6 2 s t h d - f n 3 6 2 s t hd - f n 3 6 2 s t h q q q q q a sa s a s a sa s ) w / c ? () w / c ? ( ) w / c ? ( ) w / c ? () w / c ? ( 7 0 . 405 . 3 18 7 . 2 1 4 2 . 50 0 15 . 0 18 7 . 1 1 7 4 . 60 0 25 . 88 7 . 7 table 7. S2018 power dissapation vs. air flow, no heat sink table 8. S2018 power dissapation vs. air flow, hts263nf-d heat sink thermal management the S2018 requires thermal management. amcc recommends the hts263nf-d heat sink available from chip coolers 333 strawberry field road warwick, ri 02886 the nf option refers to 'no fan'. the hts263nf-d package outline drawing is provided in figure 9. airflow requirement is determined by pd = (t j max - t a max ) / q ja , q ja = q jc + q ca where t j max is the maximum junction temperature t a max is the maximum ambient temperature q ja is the thermal dissipation coefficient from junction to ambient q jc is the thermal dissipation coefficient from junction to case q ca is the thermal dissipation coefficient from case to ambient (if a heat sink is used, this is q sa - sink to ambient) tables 7 and 8 show max package power vs. airlfow, calculated using the equation above with t j max = 125 ?c and t a max = 70 ?c. in order to successfully use the S2018, the max package power must exceed the specified max power dissipation of the device, which is determined by the output swing setting (see table 10). phone: 401-739-7600 or 800-227-0254 fax: 401-732-6119 web: www.chipcoolers.com
15 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d figure 9. S2018 hts263nf-d heat sink outline drawing note: 1. heatsink material: aluminum 2. mounting clip material: 50% glass filled ppa plastic 3. heatsink finish: black anodize 4. thermal interface: cool link 5. tolerance: .005" unless otherwise noted.
16 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 9. absolute maximum ratings table 10. recommended operating conditions r e t e m a r a pn i mp y tx a ms t i n u s a i b r e d n u e r u t a r e p m e t t n e i b m a0 4 -0 7c ? s a i b r e d n u e r u t a r e p m e t n o i t c n u j5 2 1c ? d n g . t . r . w n i p r e w o p y n a n o e g a t l o v5 3 1 . 33 . 35 6 4 . 3v n i p t u p n i l c e p v l y n a n o e g a t l o vv c c 2 -v c c v n i p t u p n i l t t v l y n a n o e g a t l o v07 4 . 3v i c c ) g n i w s t u p t u o v m 0 4 2 h t i w ( t n e r r u c y l p p u s9 8 . 04 1 . 1a i c c ) g n i w s t u p t u o v m 0 4 4 h t i w ( t n e r r u c y l p p u s0 . 17 2 . 1a i c c ) g n i w s t u p t u o v m 0 0 6 h t i w ( t n e r r u c y l p p u s9 0 . 19 4 . 1a i c c ) g n i w s t u p t u o v m 0 8 7 h t i w ( t n e r r u c y l p p u s9 1 . 12 5 . 1a i c c ) g n i w s t u p t u o v m 0 4 9 h t i w ( t n e r r u c y l p p u s8 2 . 12 6 . 1a i c c ) g n i w s t u p t u o v m 0 0 1 1 h t i w ( t n e r r u c y l p p u s7 3 . 13 7 . 1a i c c ) g n i w s t u p t u o v m 0 6 2 1 h t i w ( t n e r r u c y l p p u s5 4 . 10 8 . 1a ) g n i w s t u p t u o v m 0 4 2 h t i w ( n o i t a p i s s i d r e w o p5 9 . 27 9 . 3w ) g n i w s t u p t u o v m 0 4 4 h t i w ( n o i t a p i s s i d r e w o p9 2 . 31 4 . 4w ) g n i w s t u p t u o v m 0 0 6 h t i w ( n o i t a p i s s i d r e w o p1 6 . 37 1 . 5w ) g n i w s t u p t u o v m 0 8 7 h t i w ( n o i t a p i s s i d r e w o p2 9 . 37 2 . 5w ) g n i w s t u p t u o v m 0 4 9 h t i w ( n o i t a p i s s i d r e w o p2 2 . 42 6 . 5w r e w o pn o i t a p i s s i d) g n i w s t u p t u o v m 0 0 1 1 h t i w (1 5 . 41 0 . 6w r e w o pn o i t a p i s s i d) g n i w s t u p t u o v m 0 6 2 1 h t i w (0 8 . 45 2 . 6w electrostatic discharge (esd) ratings the S2018 is rated to the following esd voltages based on the human body model: 1. all pins are rated at 100 v. r e t e m a r a pn i mp y tx a ms t i n u e r u t a r e p m e t e g a r o t s5 6 -0 5 1c ? d n g . t . r . w n i p r e w o p y n a n o e g a t l o v5 . 0 -4v n i p t u p n i l c e p v l y n a n o e g a t l o v0v c c v n i p t u p n i l t t v l y n a n o e g a t l o v5 . 0 -7 4 . 3v t n e r r u c e c r u o s t u p t u o l m c d e e p s h g i h0 3a m
17 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 11. input and output dc characteristics r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c s t u p n i l t t v l v h i e g a t l o v h g i h t u p n i2 v c c 5 . 0 + vv c c x a m = v l i e g a t l o v w o l t u p n i08 . 0vv c c x a m = i h i t n e r r u c h g i h t u p n i0 5a v 4 . 2 = n i v i l i t n e r r u c w o l t u p n i0 0 5 -a v 5 . 0 = n i v d v t s y h s i s e r e t s y h f o e d u t i n g a m0 2 1v m s t u p n i l c e p v l v d i e g a t l o v t u p n i l a i t n e r e f f i d g n i w s 0 0 20 0 4 1p p v m. 0 1 e r u g i f e e s v s a i b r o f t n i o p s a i b e g a t l o v l a n r e t n i s t u p n i l a i t n e r e f f i d e h t v c c 0 . 1 - v c c 4 8 . 0 - v c c 5 7 . 0 - v. 0 1 e r u g i f e e s i h i t n e r r u c h g i h t u p n i5 1a mv d i x a m = i l i t n e r r u c w o l t u p n i5 1 -a mv d i x a m = r f f i d e c n a d e p m i t u p n i l a i t n e r e f f i d0 80 0 10 2 1 w s t u p t u o l m c v h o e g a t l o v h g i h t u p t u o l m c ) g n i w s t u p t u o v m 0 4 2 h t i w ( v c c 0 2 . 0 - v c c 1 0 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v l o e g a t l o v w o l t u p t u o l m c ) g n i w s t u p t u o v m 0 4 2 h t i w ( v c c 5 3 . 0 - v c c 5 0 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v h o e g a t l o v h g i h t u p t u o l m c ) g n i w s t u p t u o v m 0 4 4 h t i w ( v c c 4 2 . 0 - v c c 4 0 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v l o e g a t l o v w o l t u p t u o l m c ) g n i w s t u p t u o v m 0 4 4 h t i w ( v c c 0 5 . 0 - v c c 5 1 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v h o e g a t l o v h g i h t u p t u o l m c ) g n i w s t u p t u o v m 0 0 6 h t i w ( v c c 9 2 . 0 - v c c 9 0 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v l o e g a t l o v w o l t u p t u o l m c ) g n i w s t u p t u o v m 0 0 6 h t i w ( v c c 5 6 . 0 - v c c 5 2 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v h o e g a t l o v h g i h t u p t u o l m c ) g n i w s t u p t u o v m 0 8 7 h t i w ( v c c 6 3 . 0 - v c c 4 1 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v l o e g a t l o v w o l t u p t u o l m c ) g n i w s t u p t u o v m 0 8 7 h t i w ( v c c 0 8 . 0 - v c c 5 3 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w (
18 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d table 11. input output dc characteristics (continued) r e t e m a r a pn o i t p i r c s e dn i mp y tx a ms t i n us n o i t i d n o c v h o e g a t l o v h g i h t u p t u o l m c ) g n i w s t u p t u o v m 0 4 9 h t i w ( v c c 2 4 . 0 - v c c 9 1 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v l o e g a t l o v w o l t u p t u o l m c ) g n i w s t u p t u o v m 0 4 9 h t i w ( v c c 0 0 . 1 - v c c 5 4 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v h o e g a t l o v h g i h t u p t u o l m c ) g n i w s t u p t u o v m 0 0 1 1 h t i w ( v c c 0 5 . 0 - v c c 0 2 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v l o e g a t l o v w o l t u p t u o l m c ) g n i w s t u p t u o v m 0 0 1 1 h t i w ( v c c 5 1 . 1 - v c c 5 5 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v h o e g a t l o v h g i h t u p t u o l m c ) g n i w s t u p t u o v m 0 6 2 1 h t i w ( v c c 5 5 . 0 - v c c 1 2 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v l o e g a t l o v w o l t u p t u o l m c ) g n i w s t u p t u o v m 0 6 2 1 h t i w ( v c c 5 3 . 1 - v c c 5 6 . 0 - v 0 0 1 w . e n i l - o t - e n i l ) . s p a c g n i l p u o c c a t u o h t i w ( v d o l a i t n e r e f f i d t u p t u o l m c g n i w s e g a t l o v 0 0 20 4 26 7 2p p v m 0 0 1 w . e n i l - o t - e n i l g n i w s t u p t u o r o f 2 e l b a t e e s . 1 1 e r u g i f e e s . s g n i t t e s v d o l a i t n e r e f f i d t u p t u o l m c g n i w s e g a t l o v 4 7 30 4 46 0 5p p v m 0 0 1 w . e n i l - o t - e n i l g n i w s t u p t u o r o f 2 e l b a t e e s . 1 1 e r u g i f e e s . s g n i t t e s v d o l a i t n e r e f f i d t u p t u o l m c g n i w s e g a t l o v 0 1 50 0 60 9 6p p v m 0 0 1 w . e n i l - o t - e n i l g n i w s t u p t u o r o f 2 e l b a t e e s . 1 1 e r u g i f e e s . s g n i t t e s v d o l a i t n e r e f f i d t u p t u o l m c g n i w s e g a t l o v 3 6 60 8 77 9 8p p v m 0 0 1 w . e n i l - o t - e n i l g n i w s t u p t u o r o f 2 e l b a t e e s . 1 1 e r u g i f e e s . s g n i t t e s v d o l a i t n e r e f f i d t u p t u o l m c g n i w s e g a t l o v 9 9 70 4 91 8 0 1p p v m 0 0 1 w . e n i l - o t - e n i l g n i w s t u p t u o r o f 2 e l b a t e e s . 1 1 e r u g i f e e s . s g n i t t e s v d o l a i t n e r e f f i d t u p t u o l m c g n i w s e g a t l o v 5 3 90 0 1 15 6 2 1p p v m 0 0 1 w . e n i l - o t - e n i l g n i w s t u p t u o r o f 2 e l b a t e e s . 1 1 e r u g i f e e s . s g n i t t e s v d o l a i t n e r e f f i d t u p t u o l m c g n i w s e g a t l o v 1 7 0 10 6 2 19 4 4 1p p v m 0 0 1 w . e n i l - o t - e n i l g n i w s t u p t u o r o f 2 e l b a t e e s . 1 1 e r u g i f e e s . s g n i t t e s r o e l g n i s ( e c n a d e p m i t u p t u o ) d e d n e 0 50 60 7 w
19 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d figure 11. differential output voltage note: v out (+) C v out (-) is the algebraic difference of the input signals. figure 10. differential input voltage note: v in (+) C v in (-) is the algebraic difference of the input signals. v in (+) v in (? v in (+) ?v in (? v swing v id = 2 x v swing v out (+) v out (? v out (+) ?v out (? v swing v od = 2 x v swing
20 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d figure 12. differential cml output to +3.3 v or +5 v pecl input ac coupled termination +3.3 v +3.3 v or +5 v 100 S2018 0.01 f 0.01 f zo=50 zo=50 +3.3 v +3.3 v 100 S2018 v cc -0.84 v 0.01 f 0.01 f zo=50 zo=50 figure 13. differential lvpecl inputs
21 S2018 17 x 17 3.2 gbit/s differential crosspoint switch july 25, 2000 / revision d xxxx xx prefix device package amcc is a registered trademark of applied micro circuits corporation. copyright ? 1999 applied micro circuits corporation d64/r96 amcc reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the informati on being relied on is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, neither do es it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. applied micro circuits corporation ? 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com c e r t i f i e d i s o 9 0 0 1 x i f e r pe c i v e de g a k c a p t i u c r i c d e t a r g e t n i C s8 1 0 2a g b s 2 5 3 C b t heat sink ordering information x

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